New Delhi [India], November 30 (ANI): Union Minister for Electronics & Information Technology, Ashwini Vaishnaw, handed over 28 chips fabricated at Semiconductor Laboratory (SCL) Mohali (including 600 bare dies & 600 packaged chips) by students from 17 academic institutions under the Chips to Start-up (C2S) Programme.
The chip handover ceremony was organised during his visit to the Semiconductor Laboratory (SCL), Mohali, on 28th November 2025 to review the progress of work and ongoing modernisation activities.
During the ceremony, the Minister stated that India is rapidly emerging as a distinctive leader in the global semiconductor landscape. “Today, institutions across the country have access to some of the world’s most advanced design technologies, creating a large-scale semiconductor development ecosystem that is unique to India.”
Director General, SCL and the team gave a detailed presentation on the chip design and fabrication process adopted under C2S Programme leveraging SCL and ChipIN Centre collaborative approach under C2S Programme, on this occasion.
In the past year alone, ChipIN Centre conducted five MPW shuttle runs, during which 122 chip designs were submitted by 46 institutions. Out of these, 56 student-designed chips have been successfully fabricated and delivered.
During the ceremony, Ashwini Vaishnaw mentioned that this progress reflects the expansive vision of the Prime Minister Narendra Modi, whose directive is clear: India must build capabilities of such scale and strength that, within the next few years, the nation establishes itself as a major global semiconductor power.
He also mentioned that the aim is to ensure that we do not depend on anyone else for our strategic needs and to become self-reliant in our strategic sectors and to use indigenous chips. In this strategy, SCL will play a very significant role.
The ChipIN Centre provides infrastructure, design tools, and mentorship to students and startups under the C2S Programme. The Centre collects chip designs from academic institutions, checks them for fabrication compliance, and sends them to SCL for production every three months. Multiple student designs are combined onto a single mask, allowing several chips to be fabricated together.
This move aims to make semiconductor design more accessible and build a strong base for India’s growing electronics ecosystem.
The initiative is part of the Ministry of Electronics and Information Technology’s (MeitY) Chips to Start-up (C2S) Programme.
The initiative has seen large participation from across the country, with over one lakh students using more than 125 lakh hours of EDA tools. Additionally, 90 startups used about 50 lakh hours of design time, bringing the total to over 175 lakh hours of tool usage, making it one of the largest centralised chip design facilities globally. (ANI)
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